ATmega128 (961732), страница 43
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A general call has been received, while the TWGCE bit in the TWAR is set.3. A data byte has been received in Master Receiver or Slave Receiver mode.By writing the TWEA bit to zero, the device can be virtually disconnected from the Twowire Serial Bus temporarily. Address recognition can then be resumed by writing theTWEA bit to one again.• Bit 5 – TWSTA: TWI START Condition BitThe application writes the TWSTA bit to one when it desires to become a master on theTwo-wire Serial Bus. The TWI hardware checks if the bus is available, and generates aSTART condition on the bus if it is free. However, if the bus is not free, the TWI waitsuntil a STOP condition is detected, and then generates a new START condition to claim206ATmega1282467M–AVR–11/04ATmega128the bus Master status.
TWSTA must be cleared by software when the START conditionhas been transmitted.• Bit 4 – TWSTO: TWI STOP Condition BitWriting the TWSTO bit to one in Master mode will generate a STOP condition on theTwo-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bitis cleared automatically. In slave mode, setting the TWSTO bit can be used to recoverfrom an error condition. This will not generate a STOP condition, but the TWI returns toa well-defined unaddressed Slave mode and releases the SCL and SDA lines to a highimpedance state.• Bit 3 – TWWC: TWI Write Collision FlagThe TWWC bit is set when attempting to write to the TWI Data Register – TWDR whenTWINT is low.
This flag is cleared by writing the TWDR Register when TWINT is high.• Bit 2 – TWEN: TWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface. When TWEN iswritten to one, the TWI takes control over the I/O pins connected to the SCL and SDApins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWIis switched off and all TWI transmissions are terminated, regardless of any ongoingoperation.• Bit 1 – Res: Reserved BitThis bit is a reserved bit and will always read as zero.• Bit 0 – TWIE: TWI Interrupt EnableWhen this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request willbe activated for as long as the TWINT flag is high.TWI Status Register – TWSRBit76543210TWS7TWS6TWS5TWS4TWS3–TWPS1TWPS0Read/WriteRRRRRRR/WR/WInitial Value11111000TWSR• Bits 7..3 – TWS: TWI StatusThese 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus.
The different status codes are described later in this section. Note that the value read from TWSRcontains both the 5-bit status value and the 2-bit prescaler value. The applicationdesigner should mask the prescaler bits to zero when checking the Status bits. Thismakes status checking independent of prescaler setting.
This approach is used in thisdatasheet, unless otherwise noted.• Bit 2 – Res: Reserved BitThis bit is reserved and will always read as zero.• Bits 1..0 – TWPS: TWI Prescaler Bits2072467M–AVR–11/04These bits can be read and written, and control the bit rate prescaler.Table 87.
TWI Bit Rate PrescalerTWPS1TWPS0Prescaler Value00101410161164To calculate bit rates, see “Bit Rate Generator Unit” on page 204. The value ofTWPS1..0 is used in the equation.TWI Data Register – TWDRBit76543210TWD7TWD6TWD5TWD4TWD3TWD2TWD1TWD0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value11111111TWDRIn Transmit mode, TWDR contains the next byte to be transmitted.
In receive mode, theTWDR contains the last byte received. It is writable while the TWI is not in the process ofshifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware.Note that the Data Register cannot be initialized by the user before the first interruptoccurs. The data in TWDR remains stable as long as TWINT is set. While data is shiftedout, data on the bus is simultaneously shifted in. TWDR always contains the last bytepresent on the bus, except after a wake up from a sleep mode by the TWI interrupt.
Inthis case, the contents of TWDR is undefined. In the case of a lost bus arbitration, nodata is lost in the transition from Master to Slave. Handling of the ACK bit is controlledautomatically by the TWI logic, the CPU cannot access the ACK bit directly.• Bits 7..0 – TWD: TWI Data RegisterThese eight bits constitute the next data byte to be transmitted, or the latest data bytereceived on the Two-wire Serial Bus.TWI (Slave) Address Register– TWARBit76543210TWA6TWA5TWA4TWA3TWA2TWA1TWA0TWGCERead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value11111110TWARThe TWAR should be loaded with the 7-bit slave address (in the seven most significantbits of TWAR) to which the TWI will respond when programmed as a slave transmitter orreceiver, and not needed in the master modes.
In multimaster systems, TWAR must beset in masters which can be addressed as slaves by other masters.The LSB of TWAR is used to enable recognition of the general call address ($00). Thereis an associated address comparator that looks for the slave address (or general calladdress if enabled) in the received serial address. If a match is found, an interruptrequest is generated.• Bits 7..1 – TWA: TWI (Slave) Address RegisterThese seven bits constitute the slave address of the TWI unit.• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit208ATmega1282467M–AVR–11/04ATmega128If set, this bit enables the recognition of a General Call given over the Two-wire SerialBus.Using the TWIThe AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all busevents, like reception of a byte or transmission of a START condition.
Because the TWIis interrupt-based, the application software is free to carry on other operations during aTWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together withthe Global Interrupt Enable bit in SREG allow the application to decide whether or notassertion of the TWINT flag should generate an interrupt request.
If the TWIE bit iscleared, the application must poll the TWINT flag in order to detect actions on the TWIbus.When the TWINT flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicatingthe current state of the TWI bus. The application software can then decide how the TWIshould behave in the next TWI bus cycle by manipulating the TWCR and TWDRRegisters.Figure 95 is a simple example of how the application can interface to the TWI hardware.In this example, a master wishes to transmit a single data byte to a slave.
This description is quite abstract, a more detailed explanation follows later in this section. A simplecode example implementing the desired behavior is also presented.ApplicationActionFigure 95. Interfacing the Application to the TWI in a Typical TransmissionTWI bus1.
Applicationwrites to TWCRto initiatetransmission ofSTART3. Check TWSR to see if STARTwas sent. Application loadsSLA+W into TWDR, and loadsappropriate control signals intoTWCR, making sure that TWINTis written to one, and TWSTA iswritten to zero.STARTTWIHardwareAction2. TWINT set.Status code indicatesSTART condition sentSLA+W5. Check TWSR to see if SLA+Wwas sent and ACK received.Application loads data into TWDR,and loads appropriate control signalsinto TWCR, making sure that TWINTis written to one.A4.
TWINT set.Status code indicatesSLA+W sendt, ACKreceivedData7. Check TWSR to see if datawas sent and ACK received.Application loads appropriatecontrol signals to send STOPinto TWCR, making sure thatTWINT is written to oneA6. TWINT set.Status code indicatesdata sent, ACK receivedSTOPIndicatesTWINT set1. The first step in a TWI transmission is to transmit a START condition. This isdone by writing a specific value into TWCR, instructing the TWI hardware totransmit a START condition. Which value to write is described later on. However,it is important that the TWINT bit is set in the value written. Writing a one toTWINT clears the flag.
The TWI will not start any operation as long as theTWINT bit in TWCR is set. Immediately after the application has cleared TWINT,the TWI will initiate transmission of the START condition.2092467M–AVR–11/042. When the START condition has been transmitted, the TWINT flag in TWCR isset, and TWSR is updated with a status code indicating that the START conditionhas successfully been sent.3. The application software should now examine the value of TWSR, to make surethat the START condition was successfully transmitted.
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