IS-GPS-705D (797936), страница 7
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The rightmost bit is the first bit out. Since the initial state of the XA Code is all1s, these first 13 chips are also the complement of the initial states of the I5 or Q5-codes.NOTE: The code phase assignments constitute inseparable pairs, each consisting of a specificI5 and a specific Q5-code phase, as shown above.29IS-GPS-705D24 Sep 2013Table 6-II.
Additional Code Phase Assignments (sheet 2 of 5)PRNSignal No.100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129XB Code Advance – Chips**I5Q55272485139933875879731968681853217578176811874378875551337213224246441424367225686119219552588479121884922971518154065664138534952315064789113659195387127976837934139330237383363261113304920490954164867161111832474399011862171382Initial XB Code State***I5Q5001010000011011011010111001101000010001100001011001101110110100110010001110001110111010111100101001001100111011011111010000011111110101010011001000001111101101101000001110101011110100101100000000111101010101000001111010001101010111100011000011101111111000010101101100100000111100001000100110111011111101111011101100111110110000100001000010100011000110110010011110001110001011101100111100011010001011000010011000011110110111100100111001100100100011100100100111110110011111011011010111110110101101101110111100100011101111011010011000101101001011001110001100110000100011110011000011000101111111001111111110110110111000110000001000000110010000001111000111101110000101011101101110011000010000100101101010100000110100110100001010101111010100101011101011110110111110111101000100010000010** XB Code Advance is the number of XB clock cycles beyond an initial state of all 1s.*** In the binary notation for the first 13 chips of the I5 and Q5 XB codes as shown in thesecolumns.
The rightmost bit is the first bit out. Since the initial state of the XA Code is all1s, these first 13 chips are also the complement of the initial states of the I5 or Q5-codes.NOTE: The code phase assignments constitute inseparable pairs, each consisting of a specificI5 and a specific Q5-code phase, as shown above.30IS-GPS-705D24 Sep 2013Table 6-II.
Additional Code Phase Assignments (sheet 3 of 5)PRNSignal No.130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159XB Code Advance – Chips**I5Q5122410921733795023197223392817692380472184112525049514770272165119778977208405480003498152657167622858374581264723701755021901479618112311148142519550917479787541863303904527271284912139637445132045596766162580632125757605796125702598Initial XB Code State***I5Q5111111110110010101110111110000010000111011000100001011111100000101011000011010001110011101110001000001111101100010101100101111011001010111110111000001011000000110001101100001100101110001101110111001010110101111100111100000011100001100011110001111101000110010110011101110000101010100111111110010010000100001000101000110111001000000011111000101100111100110100111011100100101111011110111110001110111011001111101110100010011110011111000101011001110010101011110111111000101011111110111101000100111000000100100001111000001001111100011010110110010101000111101001000100001000001001011010111101010010010101100011011100001000010001111000001011110011101010000100100101111100111000011101111101101110101110110010010110111010101110010010010001101000110001001110000110101001000101000000111101110** XB Code Advance is the number of XB clock cycles beyond an initial state of all 1s.*** In the binary notation for the first 13 chips of the I5 and Q5 XB codes as shown in thesecolumns.
The rightmost bit is the first bit out. Since the initial state of the XA Code is all1s, these first 13 chips are also the complement of the initial states of the I5 or Q5-codes.NOTE: The code phase assignments constitute inseparable pairs, each consisting of a specificI5 and a specific Q5-code phase, as shown above.31IS-GPS-705D24 Sep 2013Table 6-II. Additional Code Phase Assignments (sheet 4 of 5)PRNSignal No.160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189XB Code Advance – Chips**I5Q52419450812342090192236854317774851106848259139585558108928947813585860586432770338136702357317147523637152802281337619867424628229183201579337601747105670796233292111502490282341196250337364597724016811639427329465419709156269231266Initial XB Code State***I5Q5111010001100101000010011001101000100111001011101111001011011101110110011011010001011101000011010110000100000111011000110001000110110011101110111010111011001011010001111101000010010100111011111100011100011101010100100110100000000110000001001101011011001011111000111100110011000110010011100000110110110011010111001100101001101000010000111001101010101111110010101011011101110010101101110010010001001111011011111111110010011110101001011000000101011110100001110100101001010001001001010011111101001000100101110010110001010101111011101100001100110000001100011111101101111110110100101101110000011100001110100011101010111110010010110111100010001000111111110000101001000011001000110110100111011111000001100110011101101011101001001110110110000001010011011011100010100100111111011101011100011** XB Code Advance is the number of XB clock cycles beyond an initial state of all 1s.*** In the binary notation for the first 13 chips of the I5 and Q5 XB codes as shown in thesecolumns.
The rightmost bit is the first bit out. Since the initial state of the XA Code is all1s, these first 13 chips are also the complement of the initial states of the I5 or Q5-codes.NOTE: The code phase assignments constitute inseparable pairs, each consisting of a specificI5 and a specific Q5-code phase, as shown above.32IS-GPS-705D24 Sep 2013Table 6-II. Additional Code Phase Assignments (sheet 5 of 5)PRNSignal No.190191192193194195196197198199200201202203204205206207208209210XB Code Advance – Chips**I5Q5704558046493241417066444583647579264276086545295051825905660632406531667542683197311515556835358986245554856567127656948374664194320867977595025125521445115154071Initial XB Code State***I5Q5111110001100010011101100011101101101100000110011011011010100101101101101010111011000010111010011100001110110010011111011010011101010001110011000110001100110111110111000100001000011000011111100001010100010110100000011100011000001010111101011010010000110011100010100001110110010001110011001111101000110100101100101000111100101111100010101111010100011011101011011010010011011100111111101101000001011100000110000011101001101100001111100001010110011101111010011100001001101011011010110111111110000110111110110010000101111001110001011101111001000100001** XB Code Advance is the number of XB clock cycles beyond an initial state of all 1s.*** In the binary notation for the first 13 chips of the I5 and Q5 XB codes as shown in thesecolumns.
The rightmost bit is the first bit out. Since the initial state of the XA Code is all1s, these first 13 chips are also the complement of the initial states of the I5 or Q5-codes.NOTE: The code phase assignments constitute inseparable pairs, each consisting of a specificI5 and a specific Q5-code phase, as shown above.6.4Operational Protocols6.4.1 Lower PRN Numbers Versus Upper PRN NumbersSee IS-GPS-200.6.4.2 PRN Number ConsistencyFor a given satellite, the same PRN number will be assigned to all operational signals (signalsmodulated by standard PRN code with data that indicates the signal health is OK).6.4.3 PRNs 33 and 37See IS-GPS-200.33IS-GPS-705D24 Sep 20136.4.4 PRNs 33 through 63See IS-GPS-200.34IS-GPS-705D24 Sep 201310 APPENDIX I.
LETTERS OF EXCEPTION10.1 Scope.Approval of this document, as well as approval of any subsequent changes to the document, canbe contingent upon a "letter of exception." This appendix depicts such "letters of exception"when authorized by the GPS Directorate.10.2 Applicable Documents.The documents listed in Section 2.0 shall be applicable to this appendix.10.3 Letters of Exception.Any letter of exception which is in force for the revision of the IS is depicted in Figure 10.3-1,10.3-2, 10.3-3, and 10.3-4.35IS-GPS-705D24 Sep 2013Figure 10.3-1.
Letters of Exception36IS-GPS-705D24 Sep 2013Figure 10.3-2. Letters of Exception (continued).37IS-GPS-705D24 Sep 2013Figure 10.3-3. Letters of Exception (continued)38IS-GPS-705D24 Sep 2013Figure 10.3-4. Letters of Exception (continued)39IS-GPS-705D24 Sep 201320 APPENDIX II. GPS NAVIGATION DATA STRUCTURE FORL5 CNAV DATA, D5(t)20.1 Scope.This appendix describes the specific GPS L5 civil navigation (CNAV) data structure denoted by,D5(t).20.2 Applicable Documents.20.2.1 Government Documents.In addition to the documents listed in paragraph 2.1, the following documents of the issuespecified contribute to the definition of the CNAV data related interfaces and form a part of thisAppendix to the extent specified herein.SpecificationsNoneStandardsNoneOther PublicationsNone20.2.2 Non-Government Documents.In addition to the documents listed in paragraph 2.2, the following documents of the issuespecified contribute to the definition of the CNAV data related interfaces and form a part of thisAppendix to the extent specified herein.SpecificationsNoneOther PublicationsNone20.3 Requirements.20.3.1 Data Characteristics.The L5 channel data stream mostly contains the same data as the L2 C channel.
The data streamshall be transmitted by the SV on the L5 channel at the rate of 50 bps with rate 1/2 FEC resultingin 100 sps.40IS-GPS-705D24 Sep 201320.3.2 Message Structure.As shown in Figures 20-1 through 20-14, the L5 CNAV message structure utilizes a basic formatof six-second 300-bit long messages. Each message contains a Cyclic Redundancy Check(CRC) parity block consisting of 24 bits covering the entire six-second message (300 bits)(reference Section 20.3.5).Message type 0 (zero) is defined to be the default message. In the event of message generationfailure, the SV shall replace each affected message type with the default message type.
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