idef3_kbsi_report (1013870), страница 12
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Thus, an activation of the left schematic in Figure 3-13 will consist of aninstance of UOB A followed by instances of both B and C. Similarly, an activation of theright schematic in Figure 3-13 will consist of an instance of UOB C preceded byinstances of both A and B; if a synchronous AND junction is used, then, to count as anactivation of the schematic, A and B must end simultaneously.ABA&&CCBFigure 3-13Sample Schematics to Illustrate Semantics of AND JunctionsA fan-out OR junction in a schematic indicates that, in an activation of the schematic,there will be an instance of at least one of the UOBs connected to the junction to theright.
Similarly, a fan-out XOR junction in a schematic indicates that, in an activation ofthe schematic, there will be an instance of exactly one of the UOBs connected to thejunction to the right. If a synchronous OR junction is used, then those instances must allmust start simultaneously. (This constraint does not apply to XOR junctions, since therecan be only one such instance in an XOR activation.) Likewise, the intuitive meaning ofa fan-in OR junction in a schematic is that, there will be at least one instance of the UOBsconnected to the junction to the left. If a synchronous OR junction is used, then, thoseinstances (if there is more than one) must all end simultaneously. Hence, an activation ofthe schematic to the left in Figure 3-14 consists of an instance of UOB A followed by aninstance of either B or C, or both B and C.
Similarly, an activation of the schematic tothe right in Figure 3-14 consists of an instance of UOB C preceded by an instance ofeither B or C, or both. If the schematics in Figure 3-14 used XOR junctions, then legalactivations would not include those in which both B and C occur in the first case and bothA and B in the second.33ABAOOCCBFigure 3-14Sample Schematics to Illustrate Semantics of OR JunctionsAlthough not a part of their actual semantics, junctions in an IDEF3 schematic oftenhave an associated “decision logic.” The decision logic of a junction determines thetiming and sequencing of the succeeding UOBs.
For OR and XOR junctions, thedecision logic documents how the process will branch in a given activation. Similar logicis captured for AND junctions (e.g., when the logic involves more than meresynchronicity). The decision logic of a junction is recorded in the elaboration for thejunction.Because of the possibility of both conjunctive and disjunctive branching in a process,branching is never indicated in IDEF3 by the presence of multiple outgoing precedencelinks from a UOB box. Such a construct is semantically ambiguous between a splitting ofthe process into concurrent subprocesses or a conditional branch in which only one (orperhaps more) of the branches is instantiated in any given activation. Use of a junction,however, makes the meaning of the branch entirely clear.
A similar ambiguity can arise ifa UOB box is the destination of multiple arrows, there are cases—often called“loopbacks”—in which this is acceptable.Junctions are always used in IDEF3 to indicate branching in a process; branching isnever indicated by linking a single source UOB with multiple destinations by means ofseveral precedence links; such schematics are semantically ambiguous between the threedifferent types of branching that are identified and — purposely! – distinguished inIDEF3.Combining JunctionsThe real power of IDEF3 lies in its ability represent processes in which multipleparallel and alternative threads are woven together into a single complex whole.
The keyto such complex representations lies in the proper use of junctions, in particular, findingthe right combinations of junctions to represent the process in question. Some of themost basic combinations are illustrated in this section.It is common to find processes in which a single thread diverges into multiple threadsand then, at some later point converges back into a single thread. In IDEF3, such34processes are represented by combining fan-out junctions and fan-in junctions. Figure 315 represents a process in which a thread diverges into parallel subprocesses and thenconverges. Because the processes run in parallel, they are represented by AND junctions.ABE23CF&1&4J1J26D5Figure 3-15Schematic with Asynchronous AND JunctionsBecause junction J1 separates UOB box 1 and boxes 2, 4, and 5, in any activation ofFigure 3-15, an instance of UOB A will complete before any of the succeeding UOBs areinstantiated. An activation of the schematic in Figure 3-15 will proceed in the followingmanner.
After an instance of UOB A, the three UOBs (B, C, and D) will be instantiated.Because J1 is asynchronous, these instances can begin in any order. Because all threepaths converge to J2, UOB F will be realized only after the instances of UOBs E, C, andD complete. Because J2 is also asynchronous, no particular order or timing of thecompletions is implied. This pattern of activation is illustrated by the plot in Figure 3-16.ABCDEFFigure 3-16Activation Plot for Figure 3-15As in Figure 3-15, the precedence link L1 shown in Figure 3-17 requires that aninstance of UOB A be completed before the UOBs signified by the succeeding boxes canbe instantiated. Synchronous logic is indicated by junction boxes having two vertical35bands (Compare Figure 3-15 and 3-17). The synchronous AND junction J1 indicatesthat, in an activation, the instances of UOBs B, C, and D will initiate simultaneously.Likewise, the synchronous AND junction J2 indicates simultaneous completion of thoseinstances of UOBs B and C and an instance of UOB E before the process continues pastthe junction to an instance of UOB F.ABE23CF&1&4J1J26D5Figure 3-17Synchronous AND JunctionsFigure 3-18 illustrates the added structure on activations imposed by the synchronicityconstraints.ABCDEFFigure 3-18Activation Plot for Figure 3-17Figure 3-19 is structured like Figure 3-15 except that junctions J1 and J2 areasynchronous OR junctions.
In an activation of the represented process, J1 indicates that,following an instance of A, one or more of the UOBs B, C, and D will be realized. Thiswill initiate one to three “threads” in the activation. Because J2 is an asynchronous ORjunction, only one of the threads needs to complete before an instance of F initiates.36ABE23CFO1J1O4J26D5Figure 3-19Asynchronous OR JunctionsFigure 3-20 illustrates the use of two synchronous OR junctions in combination. Thefan-out OR junction implies that, in an activation, instances of one or more of the UOBsB, C, and D will start after an instance of A.ABE23CFO1J1O4J26D5Figure 3-20Synchronous OR JunctionsBecause the junction is synchronous, when more than one UOB is instantiated, theinstances occur simultaneously.
If one of these is an instance of UOB B, it will befollowed by an instance of UOB E, which will compete simultaneously with whateverinstances initiated along with the instance of UOB B, as illustrated by the left activationplot in Figure 3-21. An activation in which UOB B is not instantiated is also illustratedby the right activation plot. Note that in the latter plot, the fact that both J1 and J2 aresynchronous forces the instances of UOBs C and D to start and complete simultaneously.37ABABCCDDEEFFFigure 3-21Activation Plots for Figure 3-20Figure 3-22 is an example of a way to combine two different types of junctions toallow more freedom in the timing and sequencing of activations.B2AE&O16CD45Figure 3-22Fan-out AND Junction Followed by a Fan-in OR JunctionAlthough instances of UOBs B and C occur after an instance of A in activations ofFigure 3-22, possible activations of the process are represented in which an instance ofone or the other may not complete, or even initiate, before the activation “proceeds”through the fan-in OR junction and an instance of E occurs.
Such activations are allowedbecause of the use of an asynchronous fan-in OR junction which governs the convergenceof the two threads. For a successful process activation, although both threads mustcomplete at some time or other, it is sufficient for only one of the threads to havecompleted prior to an instance of E. Figure 3-23 provides plots of three basic activationpatterns permitted by Figure 3-22.
The leftmost plot exhibits a pattern that would bepermitted if the OR junction were an AND junction instead (or, equivalently, if the ORjunction were synchronous). In the leftmost plot, instances of both B and D (hence alsoC) complete before an instance of E. In the middle plot, an instance of E begins before an38instance of B completes (or even starts), and in the right plot, an instance of E beginsbefore an instance of D completes.ABCABCABCDEDEDEFigure 3-23Activation Plots for Figure 3-22Of course, additional constraints on activations could further narrow the class ofpossible activations; e.g., one could require that the instance of B in an activation alwaysbegin before the instance of E completes.
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