Диссертация (Исследование и разработка методов автоматического вывода геометрических ограничений с использованием декларативного программирования и формальных методов), страница 23
Описание файла
Файл "Диссертация" внутри архива находится в папке "Исследование и разработка методов автоматического вывода геометрических ограничений с использованием декларативного программирования и формальных методов". PDF-файл из архива "Исследование и разработка методов автоматического вывода геометрических ограничений с использованием декларативного программирования и формальных методов", который расположен в категории "". Всё это находится в предмете "технические науки" из Аспирантура и докторантура, которые можно найти в файловом архиве РТУ МИРЭА. Не смотря на прямую связь этого архива с РТУ МИРЭА, его также можно найти и в других разделах. , а ещё этот архив представляет собой кандидатскую диссертацию, поэтому ещё представлен в разделе всех диссертаций на соискание учёной степени кандидата технических наук.
Просмотр PDF-файла онлайн
Текст 23 страницы из PDF
320–324.93. Makino Kazuhisa, Uno Takeaki. New algorithms for enumerating all maximalcliques // Scandinavian Workshop on Algorithm Theory / Springer. — 2004. —Pp. 260–272.94. Avis David, Fukuda Komei. Reverse search for enumeration // Discrete AppliedMathematics. — 1996. — Vol. 65, no. 1.
— Pp. 21–46.95. Johnson David S, Yannakakis Mihalis, Papadimitriou Christos H. On generating all maximal independent sets // Information Processing Letters. — 1988. —Vol. 27, no. 3. — Pp. 119–123.96. McCluskey Edward J. Logic design principles with emphasis on testable semicustom circuits. — 1986.11797. Rudell Richard, Sangiovanni-Vincentelli Alberto. Logic synthesis for VLSI design: Ph.D. thesis / University of California, Berkeley.
— 1989.98. Coudert Olivier. Two-level logic minimization: an overview // Integration, theVLSI journal. — 1994. — Vol. 17, no. 2. — Pp. 97–140.99. Fiser Petr, Hlavicka Jan. Implicant Expansion Methods Used in The Boom Minimizer // IEEE DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITSAND SYSTEMS WORKSHOP / Citeseer. — 2001.100.
Fiser Petr, Kubátová Hana. Flexible two-level Boolean minimizer BOOM-IIand its applications // 9th EUROMICRO Conference on Digital System Design(DSD’06) / IEEE. — 2006. — Pp. 369–376.101. Sapra Samir, Theobald Michael, Clarke Edmund. SAT-based algorithms for logicminimization // Computer Design, 2003. Proceedings. 21st International Conference on / IEEE. — 2003. — Pp. 510–517.102. Savran Ibrahim, Bakos Jason D. GPU acceleration of near-minimal logic minimization // Proceedings of Symposium on Application Accelerators in HighPerformance Computing / Citeseer. — 2010.103. Logic minimization algorithms for VLSI synthesis / Robert K Brayton,Gary D Hachtel, Curt McMullen, Alberto Sangiovanni-Vincentelli.
— SpringerScience & Business Media, 1984. — Vol. 2.104. Rudell Richard L. Multiple-valued logic minimization for PLA synthesis. — 1986.105. Suto G. Rule agnostic routing by using design fabrics // Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE / IEEE. — 2012.
— Pp. 471–475.106. Bhanushali Kirti Narayan. Design Rule Development for FreePDK15: An OpenSource Predictive Process Design Kit for 15nm FinFET Devices. — 2014.107. Lai Kafai, Erdmann Andreas. Extending VLSI and Alternative Technology withOptical and Complementary Lithography. — 2016.108. Layout decomposition for triple patterning lithography / Bei Yu, Kun Yuan,Duo Ding, David Z Pan // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
— 2015. — Vol. 34, no. 3. — Pp. 433–446.118109. EUV resolution enhancement techniques (RETs) for k1 0.4 and below /Stephen Hsu, Rafael Howell, Jianjun Jia et al. // SPIE Advanced Lithography /International Society for Optics and Photonics. — 2015. — Pp. 94221I–94221I.110. Rovner Vyacheslav V. Circuit-Layout Co-optimization for Extremely Regular Design Fabrics in Nanoscale ICs: Ph.D.
thesis / Carnegie Mellon University Pittsburgh, PA. — 2010.111. Open Cell Library in 15nm FreePDK Technology / Mayler Martins,Jody Maick Matos, Renato P Ribas et al. // Proceedings of the 2015 Symposium on International Symposium on Physical Design / ACM. — 2015.
—Pp. 171–178.112. Bhanushali Kirti, Davis W Rhett. FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology // Proceedings of the 2015 Symposium on International Symposium on Physical Design / ACM. — 2015. —Pp. 165–170.113. Library Architecture Challenges for Cell-Based Design. / Barbara Chappell,Amanda Duncan, Kiran Ganesh et al. // Intel Technology Journal. — 2004. —Vol. 8, no.
1.114. A 5–10GHz SiGe BiCMOS FPGA with new configurable logic block / Chao You,Jong-Ru Guo, Russell P Kraft et al. // Microprocessors and Microsystems. —2005. — Vol. 29, no. 2. — Pp. 121–131.115. Zhao X-A, Kolawa E, Nicolet M-A. Reaction of thin metal films with crystallineand amorphous Al2O3 // Journal of Vacuum Science & Technology A. — 1986.— Vol. 4, no. 6. — Pp. 3139–3141.116. Hu Xiao Ming. Photolithography technology in electronic fabrication. — 2015.117.
An overview of resist processing for deep-UV lithography. / Omkaram Nalamasu,May Cheng, Allen G Timko et al. // Journal of Photopolymer Science and Technology. — 1991. — Vol. 4, no. 3. — Pp. 299–318.118. La Fontaine Bruno. Lasers and Moore’s law // SPIE Professional, October.
—2010. — P. 20.119119. A 45nm logic technology with high-k+ metal gate transistors, strained silicon,9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging /Kaizad Mistry, C Allen, Chris Auth et al. // 2007 IEEE International ElectronDevices Meeting / IEEE. — 2007.
— Pp. 247–250.120. Geppert Linda. Chip making’s wet new world // IEEE Spectrum. — 2004. —Vol. 41, no. 5. — Pp. 29–33.121. Schellenberg Frank. A little light magic [optical lithography] // IEEE Spectrum.— 2003. — Vol. 40, no. 9. — Pp. 34–39.122.
Automated optical proximity correction: a rules-based approach / Oberdan W Otto, Joseph G Garofalo, KK Low et al. // SPIE’s 1994 Symposium onMicrolithography / International Society for Optics and Photonics. — 1994. —Pp. 278–293.123. The selection and creation of the rules in rules-based optical proximity correction / Rui Shi, Yici Cai, Xianlong Hong et al. // ASIC, 2001. Proceedings. 4thInternational Conference on / IEEE. — 2001. — Pp. 50–53.124. Practical method for full-chip optical proximity correction / J Chen,Thomas Laidig, Kurt Wampler, Roger Caldwell // Microlithography 97 /International Society for Optics and Photonics.
— 1997. — Pp. 790–803.125. Stirniman John, Rieger Michael. Fast proximity correction with zone sampling //SPIE’s 1994 Symposium on Microlithography / International Society for Opticsand Photonics. — 1994. — Pp. 294–301.126. Stirniman John, Rieger Michael, Gleason Robert. Quantifying proximity and related effects in advanced wafer processes // SPIE’s 1995 Symposium on Microlithography / International Society for Optics and Photonics. — 1995. —Pp. 252–260.127. Stirniman John, Rieger Michael. Spatial-filter models to describe IC lithographicbehavior // Microlithography’97 / International Society for Optics and Photonics.— 1997.
— Pp. 469–478.120128. Cobb Nicolas, Zakhor Avideh. Large-area phase-shift mask design // SPIE’s 1994Symposium on Microlithography / International Society for Optics and Photonics.— 1994. — Pp. 348–360.129. Cobb Nicolas, Zakhor Avideh. Fast, low-complexity mask design // SPIE’s 1995Symposium on Microlithography / International Society for Optics and Photonics.— 1995. — Pp. 313–327.130. Cobb Nicolas, Zakhor Avideh. Fast sparse aerial-image calculation for OPC // 15thAnnual BACUS Symposium on Photomask Technology and Management’95 /International Society for Optics and Photonics. — 1995. — Pp.
534–545.131. Matsunawa Tetsuaki, Yu Bei, Pan David. Optical proximity correction with hierarchical Bayes model // SPIE Advanced Lithography / International Society forOptics and Photonics. — 2015.132. Optical Proximity Correction Using a New Hyper Error Estimation Method / PeiShan Wu, Yu-Cheng Lin, Jui-Hung Hung, Tsai-Ming Hsieh // Proceedings of the2nd International Conference on Computer Science and Electronics Engineering /Atlantis Press. — 2013.133. Awad Ahmed, Takahashi Atsushi, Kodama Chikaaki. A fast manufacturabilityaware Optical Proximity Correction (OPC) algorithm with adaptive wafer imageestimation // 2016 Design, Automation & Test in Europe Conference & Exhibition(DATE) / IEEE.
— 2016. — Pp. 49–54.134. Patterning options for N7 logic: prospects and challenges for EUV / Eelco van Setten, Friso Wittebrood, Eleni Psara et al. // 31st European Mask and LithographyConference / International Society for Optics and Photonics. — 2015.135. 5nm Test Lights Litho Path. — http://www.eetimes.com/document.asp?doc_id=1327919.
— Accessed: 2016-05-27.136. Yaung Dun-Nian, Wuu Shou-Gwo, Chao Li-chih, Huang Kuo. Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits. — 2000. — US Patent 6,165,880.137. Studies of plasma surface interactions during short time plasma etching of 193 and248nm photoresist materials / Xuefeng Hua, S Engelmann, GS Oehrlein et al.
//121Journal of Vacuum Science & Technology B. — 2006. — Vol. 24, no. 4. —Pp. 1850–1858.138. Fabrication of sub-10-nm silicon nanowire arrays by size reduction lithography /Yang-Kyu Choi, Ji Zhu, Jeff Grunes et al. // The Journal of Physical Chemistry B.— 2003. — Vol. 107, no. 15.139. Multitechnique metrology methods for evaluating pitch walking in 14 nm andbeyond FinFETs / Robin Chao, Kriti Kohli, Yunlin Zhang et al.
// Journal of Micro/Nanolithography, MEMS, and MOEMS. — 2014. — Vol. 13, no. 4.140. Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme / H Tomizawa, St Chen, D Horak et al. // Interconnect Technology Conference and 2011 Materials for AdvancedMetallization (IITC/MAM), 2011 IEEE International / IEEE. — 2011. — Pp. 1–3.141. Ban Yongchan, Pan David. Self-aligned double-patterning layout decompositionfor two-dimensional random metals for sub-10-nm node design // Journal of Micro/Nanolithography, MEMS, and MOEMS. — 2015. — Vol.
14, no. 1.142. Spacer-is-dielectric-compliant detailed routing for self-aligned double patterninglithography / Yuelin Du, Qiang Ma, Hua Song et al. // Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE / IEEE. — 2013. — Pp. 1–6.143. EUV litho keeps progressing, keeps slipping. — http://www.eetimes.com/document.asp?doc_id=1256589. — Accessed: 2016-05-27.144. Carlson Andrew, Liu Tsu-Jae. Negative and iterated spacer lithography processesfor low variability and ultra-dense integration // SPIE Advanced Lithography /International Society for Optics and Photonics. — 2008.145.
Chen Frederick. Methods for forming patterns. — 2011. — US Patent 7,919,413.146. Subresolution assist features in extreme ultraviolet lithography / Deniz Civay,Erik Verduijn, Chris Clifford et al. // Journal of Micro/Nanolithography, MEMS,and MOEMS. — 2015.
— Vol. 14, no. 2.147. Many ways to shrink: The right moves to 10 nanometer and beyond.—https://staticwww.asml.com/doclib/investor/asml_3_Investor_Day-Many_ways_to_shrink_MvdBrink1.pdf. — Accessed: 2016-05-27.122148. EUV lithography scanner for sub-8nm resolution / Jan van Schoot, Koen van Ingen Schenau, Chris Valentin, Sascha Migura // SPIE Advanced Lithography / International Society for Optics and Photonics. — 2015.149. Chen Yijian, Cheng Qi, Kang Weiling. Mandrel and spacer engineering based selfaligned triple patterning // SPIE Advanced Lithography / International Society forOptics and Photonics. — 2012.150. Imaging performance and challenges of 10nm and 7nm Logic nodes with 0.33NA EUV / Eelco van Setten, Guido Schiffelers, Eleni Psara et al.