Лекция 4 - MIPS_3 (Слайды лекций)
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A Simplified MIPS Processor inVerilogData Memory• module DM(MemRead, MemWrite, ABUS,DIN, DATABUS);– MemWrite: Nothing happens if 0. If 1, the memory atlocation ABUS will be written with DIN.– ABUS: At any moment, the data at location ABUS willappear at DATABUS.– MemRead: Not used.Data Memory• Address bus: 8 bits.• Data bus: 32 bits.
Each memory location holds32 bits.Data Memory• Init the contents in data memory with anyvalue you like:initialbeginfor (i=0; i <= DM_ADDR_MAX_m1; i = i + 1)ram[i] = i*10 + 1;endInstruction Memory• module IM(CSB,WRB,ABUS,DATABUS);– CSB: chip select. If 0, selected. If 1, not selected.– WRB: Not used.– ABUS: Address bus. At any moment, if chip is selected,the data at location ABUS will appear at DATABUS.Instruction Memory• Address bus: 8 bits.• Data bus: 32 bits. Each memory location holds32 bits.Instruction Memory• The most straightforward way of loading a program:ram[0]ram[1]ram[2]ram[3]ram[4]ram[5]ram[6]ram[7]ram[8]ram[9]==========32'b00100000000000000000000000000000;32'b00100000001000010000000000000001;32'b00100000010000100000000000000010;32'b00100000011000110000000000000011;32'b00000000000000000000000000000000;32'b00000000000000000000000000000000;32'b00000000000000000000000000000000;32'b00000000000000000000000000000000;32'b00000000000000000000000000000000;32'b00000000000000000000000000000000;////////////////////addiaddiaddiaddinopnopnopnopnopnop$0,$1,$2,$3,$0,$1,$2,$3,0123Get The Next PCmodule getNextPC (PCSrc, currPC, offset, out);parameter MIPS_PC_WIDTH_m1 = 7;input PCSrc;input [MIPS_PC_WIDTH_m1:0] offset;input [MIPS_PC_WIDTH_m1:0] currPC;output reg [MIPS_PC_WIDTH_m1:0] out;always @(PCSrc, currPC, offset)if (PCSrc == 0)out <= currPC + 1;elseout <= currPC + 1 + offset;endmodulePC• module MIPSPC(clk, newPC, PC);• Just an 8-bit D-flip-flop.Register File• module MIPSREG(clk, RegWrite, ReadAddr1,ReadAddr2, WriteAddr, ReadData1, ReadData2,WriteData);– Just as what specified in the book.– RegWrite: If 0, disabling write.
If 1, register WriteAddr registerWriteAddr will be overwritten with WriteData.– At any time, ReadData1 is the content of reg ReadAddr1, andReadData2 is the content of reg ReadAddr2.ALUmodule MIPSALU (ALUctl, A, B, ALUOut, Zero);input [3:0] ALUctl;input [31:0] A,B;output reg [31:0] ALUOut;output Zero;assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goesanywherealways @(ALUctl, A, B) //reevaluate if these changecase (ALUctl)0: ALUOut <= A & B;1: ALUOut <= A | B;2: ALUOut <= A + B;6: ALUOut <= A - B;7: ALUOut <= A < B ? 1:0;12: ALUOut <= ~(A | B); // result is nordefault: ALUOut <= 0; //default to 0, should not happen;endcaseendmoduleSign Extensionmodule SignExtend (in, out);input [15:0] in;output [31:0] out;assign out[15:0] = in[15:0];assign out[31:16] = in[15];endmoduleTwo-to-one Selectormodule STwoToOne32 (sel, in0, in1, out);input sel;input [31:0] in0, in1;output reg [31:0] out;always @(sel, in0, in1)if (sel == 0)out <= in0;elseout <= in1;endmoduleControl• module MIPSCtrl (instr, RegDst, ALUSrc, MemToReg,RegWrite, MemWrite, MemRead, branch, ALUCtrl);• Take the 32-bit instruction, generate the control signals.Data Path Setup According toSupported instructions• add, sub, addi, lw, sw, beq.Stepping through the program• The clock is set to be 200 time units.
Run 200every time.• Check the values of the wires in the waveform• Check the content of the registers and datamemories in the memory windows.The waveform after two instructions00100000000000000000000000000000;00100000001000010000000000000001;// addi $0, $0, 0// addi $1, $1, 1Supporting a new instruction• With the current data path, can we support anew instruction?lwr $rs, $rt, $rd• What it does is to read from data memory at$rs-$rt, and write it to $rd• Suppose its opcode is 000001.Supporting a new instructionelse if (instr[31:26] == 6'b000001) //lwrbeginRegDst <= 1;ALUSrc <= 0;MemToReg <= 1;RegWrite <= 1;MemRead <= 1;MemWrite <= 0;branch <= 0;ALUCtrl <= 4'b0110;end.
